The dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits is the metal-oxide-semiconductor field effect transistor (MOSFET) technology. Reduction in the size of MOSFETs has provided continued improvement in speed, performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increasingly interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel.
Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-30 nm regime, approaches involving the use of fin field-effect transistors (finFETs) are being investigated to improve the short channel effects.
Generally, fins are produced by etching a trench in a silicon substrate and filling the trench with an oxide. The surface of the substrate is planarized and the oxide is recessed through etching to expose the silicon fin. A gate dielectric layer and a conductive gate layer are formed overlying the fins. This process, however, results in identical fin heights for each fin.
As a result, a structure of and method for forming semiconductor devices having different fin heights are needed.